1. Field of the Invention
The embodiments of the invention generally relate to metal oxide semiconductor field effect transistors (MOSFETS), and, more particularly, to an improved method of forming a stressing layer without damaging the underlying transistor and without compromising its performance.
2. Description of the Related Art
Modern day logic transistors are exposed to plasma damage at many stages of processing. This plasma damage is aggravated due to the usage of more plasma processing steps, such as with the introduction of plasma generated stress liners which improve logic performance by carrier hole mobility enhancement. High-power high density plasma-based films (HDP) have an advantage over conventional plasma enhanced chemical vapor deposition (PECVD) films, because they reduce the performance offset between isolated and nested devices. However, exposing transistors to high-power plasma processes can sometimes affect the overall reliability of the transistors. In fact there is sometimes a remarkable decrease in reliability and performance in terms of thick gate oxide breakdown, enhanced bias temperature instability (NBTI), and other problems because of such high-power plasma-based films.